1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device having an SOI (Silicon On Insulator) structure, and a manufacturing method thereof.
2. Background of the Invention
FIGS. 37 through 47 are longitudinal cross-sectional views of a semiconductor device having a conventional SOI structure, showing successive stages of a manufacturing process. Using the drawings, we will describe the structure of a conventional semiconductor device at each step.
First prepared is an SOI substrate 130A shown in FIG. 37, formed for example by an SIMOX (Separation by implanted Oxygen) method. As shown, the SOI substrate 130A comprises a buried oxide film 102 and an SOI layer of single crystalline silicon 103A formed sequentially on one surface of the silicon substrate 101. The SOI substrate 130A may be formed by other methods such as wafer bonding, as long as having such a structure.
Next, as shown in FIG. 38, the surface of the SOI layer 103A in the SOI substrate 130A is oxidized to form a silicon oxide film 104A having a thickness of about 100 xc3x85 to 300 xc3x85. And a silicon nitride film 105A having a thickness of about 2000 xc3x85 is deposited thereon. The silicon oxide film 104A can be formed by other methods such as CVD using TEOS (Tetra Ethyl Ortho Silicate). The silicon oxide film 104A and the silicon nitride film 105A are then patterned by photolithography and dry etching to form a silicon oxide film (hereinafter referred to also as an xe2x80x9cunderlying oxide filmxe2x80x9d) 104 and a silicon nitride film 105 as shown in FIG. 39. A region where the underlying oxide film 104 and the silicon nitride film 105 are formed is referred to as an active region 151, while a region except the active region 151 is referred to as an isolation region 152.
After that, the SOI layer 103A is anisotropically etched with the silicon nitride film 105 used as a mask, to form an SOI layer 103 as shown in FIG. 40. The silicon substrate 101, the buried oxide film 102, and the SOI layer 103 after this etching are generically referred to as an xe2x80x9cSOI substrate 130xe2x80x9d.
Then, as shown in FIG. 41, a silicon oxide film 108A having a thickness at least larger than a difference in level between the active region 151 and the isolation region 152 (about 5000 xc3x85, for example) is deposited to cover the overall exposed surface of the SOI substrate 130.
The silicon oxide film 108A is then polished for planarization by a CMP (Chemical Mechanical Polishing) method, as shown in FIG. 42, to the extent that the silicon nitride film 105 is exposed. After the polishing, part of the silicon oxide film 108A remains on the isolation region 152 of the buried oxide film 102, as a silicon oxide film 108B.
Next, the silicon nitride film 105 is removed by phosphoric acid of about 160xc2x0 C. (see FIG. 43).
Then, after channel implantation through the underlying oxide film 104, the film 104 is removed by hydrofluoric acid. At the same time, the silicon oxide film 108B is etched to a predetermined depth to form a silicon oxide film 108 shown in FIG. 44.
After that, as shown in FIG. 45, a silicon oxide film 109A having a thickness of about 70 xc3x85 is formed to cover the exposed surface 103S (cf. FIG. 44) of the SOI layer 103. Subsequently, an electrode layer 110A having a thickness of about 2000 xc3x85 is formed as shown in FIG. 46. The silicon oxide film 109A and the electrode layer 110A are then patterned by photolithography and dry etching to form a gate oxide film 109 and a gate electrode 110 shown in FIG. 47. Then, semiconductor regions 120A and 120B each forming a source or drain region are formed by implanting an impurity into a predetermined region. After an interlayer oxide film 111 is formed across the surface of the SOI substrate 130, contact holes CAP and CBP are formed in the surface of the interlayer oxide film 111 so as to reach the source or drain regions 120A and 120B, respectively, as shown in FIG. 47. The contact holes CAP and CBP are filled with a wiring material, such as aluminum, to form wires 112A and 112B, respectively. In this manner, the SOI/MOSFET shown in FIG. 47 is obtained.
According to the manufacturing process described above, when the underlying oxide film 104 in the semiconductor device shown in FIG. 43 is removed by etching using hydrofluoric acid, the silicon oxide film 108B is etched at the same time. Since the etch rate of the silicon oxide film 108B is larger than that of the underlying oxide film 104 formed by thermal oxidation, the silicon oxide film 108B will be overetched in the vicinity of the Si/SiO2 interface between the SOI layer 103 and the silicon oxide film 108B. This makes that portion of the silicon oxide film 108B smaller in height (thickness) than the SOI layer 103. Such a portion will be referred to as a depression 200.
FIG. 48 is a longitudinal cross-sectional view taken along a line Xxe2x80x94X in FIG. 47, when viewed from the direction indicated by the arrow. FIG. 49 is an enlarged cross-sectional view showing a vicinity of the depression 200 in FIG. 48 (a region AP indicated by dashed lines).
In the semiconductor device with the depression 200 shown in FIG. 44, when the silicon oxide film 109A and the electrode layer 110A are sequentially formed on the surface 103S of the SOI layer 103, their shapes will be affected by the depression 200 as shown in FIG. 46. Accordingly, the depression 200 will affect the shapes of the gate oxide film 109 and the gate electrode 110 which are obtained by patterning the silicon oxide film 109A and the conductive material 110A, as shown in FIG. 48.
A conventional MOSFET 140 with the depression 200, as shown in FIG. 49, comprises not only a real MOSFET 140S but also a parasitic MOSFET 140T formed at the end portion of the SOI layer 103. More specifically, the real MOSFET 140S has a gate electrode structure comprising a gate oxide film 109S and a gate electrode 110S formed on the surface 103S of the SOI layer 103, and the parasitic MOSFET 140T has a gate electrode structure comprising a gate oxide film 109T and a gate electrode 110T formed on the side surface 103T of the SOI layer 103.
Since an electric field is applied both to the real MOSFET 140S and to the parasitic MOSFET 140T, a large electric field is applied to the end portion of the SOI layer 103 in the conventional MOSFET 140. This causes, with lower voltage than the threshold value of the real MOSFET 140S, a flow of drain current at the end portion of the conventional MOSFET 140 (problem (1)). That is, there has been a problem that the conventional MOSFET 140 with the depression 200 cannot ensure designed device characteristics due to the parasitic MOSFET 140T.
Further, a strong electric field to be applied to the end portion of the conventional MOSFET 140 is likely to cause degradation in insulation of the gate oxide film 109, namely, the gate oxide films 109T and 109S, in the vicinity of the end portion (problem (2)). This may cause improper operation of the conventional MOSFET 140 even with relatively low gate voltage.
Further, in the conventional MOSFET 140 as shown in FIG. 49, the SOI layer 103 and the silicon oxide film 108 under the bottom of the depression form an Si/SiO2 interface. Since the silicon oxide film 108 is a film formed by deposition such as CVD, the Si/SiO2 interface has relatively a lot of interface states. Thus, a large difference in potential between the bottom of the depression 200 and the SOI layer 103 is likely to cause degradation in insulation of the silicon oxide film 108 at the Si/SiO2 interface (problem (3)). Such degradation in insulation at the interface equals degradation in insulation of the parasitic MOSFET 140T, thereby resulting in degradation in insulation of the conventional MOSFET 140 itself. Consequently, the conventional MOSFET 140 will not function normally.
A first aspect of the present invention is directed to a semiconductor device comprising: a first insulating layer; a semiconductor layer formed on a first region of a surface of the first insulating layer; a second insulating layer formed on a second region of the surface of the first insulating layer, the second region being adjacent to the first region; a third insulating layer formed on a peripheral portion of the semiconductor layer, and integrally joined to the second insulating layer adjacent thereto at its end portion; a fourth insulating layer formed across a third region of a surface of the semiconductor layer, and integrally joined to the third insulating layer at its end portion which intersects with the longitudinally extending the third insulating layer, the third region being opposed to the first region and surrounded by the peripheral portion; a control electrode layer formed on a surface of the fourth insulating layer and on a portion where the third insulating layer is integrally joined to the fourth insulating layer; a first semiconductor region having a first impurity of a predetermined conductivity type, formed in a fourth region of the surface of the semiconductor layer, the fourth region being adjacent to the third region; and a second semiconductor region having a second impurity of the predetermined conductivity type, formed in a fifth region of the surface of the semiconductor layer, the fifth region being adjacent to the third region so as to sandwich the third region between the fourth region and itself. The thickness of the peripheral portion of the semiconductor layer decreases as closer to the end portion of the semiconductor layer, while the thickness of the third insulating layer increases as closer to the end portion of the semiconductor layer.
According to a second aspect of the present invention, the semiconductor device of the first aspect further comprises: a fifth insulating layer formed on the end portion of the semiconductor layer, and on the second region of the surface of the first insulating layer in the vicinity of the end portion of the semiconductor layer. The fifth insulating layer has a first side surface joined to the end portion of the semiconductor layer, and a second side surface opposed to the first side surface. The second side surface is integrally joined to a side surface of the second insulating layer on the side of the semiconductor layer. On the top surface of the fifth insulating layer which is opposed to the bottom surface forming an interface along with the surface of the first insulating layer, the third insulating layer is extended from the end portion of the semiconductor layer. The end portion of the third insulating layer is integrally joined to the side surface of the second insulating layer.
According to a third aspect of the present invention, in the semiconductor device of the first aspect, the second insulating layer comprises a sixth insulating layer and a seventh insulating layer. The sixth insulating layer is formed at least on the end portion of the semiconductor layer and on the end portion of the third insulating layer, and integrally joined to the third insulating layer. The seventh insulating layer formed to be adjacent to and integrally joined to the sixth insulating layer.
A fourth aspect of the present invention is directed to a semiconductor device having a trench isolation structure comprising a first insulating layer, a semiconductor layer formed on a first region of a surface of the first insulating layer, and a second insulating layer formed on a second region surrounding the first region to be adjacent to the semiconductor layer. In the device, the second insulating layer is formed on a peripheral portion of the semiconductor layer. Further, a thickness of the peripheral portion of the semiconductor layer decreases as closer to an end portion of the semiconductor layer, while a thickness of the second insulating layer formed on the peripheral portion of the semiconductor layer increases as closer to the end portion of the semiconductor layer.
A fifth aspect of the present invention is directed to a method of manufacturing a semiconductor device. The method comprises: a first step of preparing an underlying layer comprising a first insulating layer and a semiconductor layer formed on a surface of the first insulating layer; a second step of forming a second insulating layer on a surface of a first portion of the semiconductor layer which is located above a first region of the surface of the first insulating layer, and forming a stopper film across a surface of the second insulating layer; a third step of forming a third insulating layer joined to the second insulating layer, on and in a surface of a second portion of the semiconductor layer which is located above a second region of the surface of the first insulating layer, the second region being adjacent to and surrounding the first region; a fourth step of forming a sidewall adjacent to a side surface of the stopper film, on a first portion of the third insulating layer which is located above a third region of the surface of the first insulating layer, and removing a second portion of the third insulating layer, the third region being within the second region and being adjacent to and surrounding the first region; a fifth step of removing the second portion of the semiconductor layer which is located above the second region except the third region; a sixth step of forming a fourth insulating layer on the second region of the first insulating layer, on a side surface of the semiconductor layer, on the side surface of the third insulating layer, and on a side surface of the sidewall; a seventh step of removing only the stopper film; and an eighth step of removing the exposed second insulating layer, the sidewall, and part of the fourth insulating layer that ranges in height from its surface to a surface of the third insulating layer adjacent to the sidewall.
According to a sixth aspect of the present invention, in the method of the fifth aspect, the sidewall consists essentially of a first sidewall and a second sidewall. Further, the fourth step comprises: a step of forming the first sidewall on the first portion of the third insulating layer and on the side surface of the stopper film; and a step of forming the second sidewall on a surface of the first sidewall to form the sidewall.
According to a seventh aspect of the present invention, in the method of the fifth aspect, the eighth step comprises: a step of forming a third sidewall on an exposed side surface of the sidewall and on a surface of the second insulating layer exposed at the seventh step, in the vicinity of the side surface of the sidewall; and a step of removing the second insulating layer, the sidewall, the third sidewall, and part of the fourth insulating layer that ranges in height from its surface to the surface of the third insulating layer adjacent to the sidewall.
In the semiconductor device of the first aspect, the third insulating layer is formed on the peripheral portion of the semiconductor layer. Further, the thickness of the peripheral portion of the semiconductor layer decreases as closer to the end portion of the semiconductor layer, while the thickness of the third insulating layer increases as closer to the end portion of the semiconductor layer. Besides, the third insulating layer is integrally joined to the adjacent second insulating layer at its end portion. Thus, the semiconductor device according to the first aspect includes no depression at the interface between the semiconductor layer and the second insulating layer as found in the conventional semiconductor device. This prevents a parasitic element to be formed at the end portion of the semiconductor device due to a depression. Therefore, the semiconductor device according to the first aspect can resolve the problems of the conventional semiconductor device that the parasitic element prevents the device from obtaining designed device characteristics and causes degradation in insulation of the fourth insulating layer.
Further, since the peripheral portion of the semiconductor layer and the third insulating layer are in such a shape as described above, concentration of an electric field in the vicinity of the peripheral portion of the semiconductor device can be relieved with voltage applied to the control electrode. Thus, it is possible to increase reliability of the fourth insulating layer, i.e., reliability of the semiconductor device itself, as compared with the conventional semiconductor device.
As described above, the semiconductor device according to the first aspect can certainly ensure the designed device characteristics as compared with the conventional semiconductor device.
In the semiconductor device of the second aspect, there exists the fifth insulating layer as well as the third insulating layer between the semiconductor layer and the second insulating layer. These second, third, and fifth insulating layers are integrally joined to each other at each interface. Thus, the semiconductor layer is not in direct contact with the second insulating layer. This certainly brings about the effect of the first aspect.
In the semiconductor device of the third aspect, the sixth insulating layer forming part of the second insulating layer is formed at least on the end portion of the semiconductor layer and on the end portion of the third insulating layer, and is integrally joined to the third insulating layer. Thus, the semiconductor layer is not in direct contact with the seventh insulating layer forming part of the second insulating layer. This certainly brings about the effect of the first aspect.
The semiconductor device of the fourth aspect can obtain the same effect as that of the first aspect.
In the manufacturing method of the fifth aspect, at the third step, the third insulating layer joined to the second insulating layer is formed on and in the surface of the second portion of the semiconductor layer, and at the fourth step, the sidewall is formed on the first portion of the third insulating layer. Thus, unlike the conventional method, it is possible to fully protect the interface between the semiconductor layer and the third or fourth insulating layer, when the fourth insulating layer is formed at the sixth step. This prevents formation of a depression at that interface, thereby preventing formation of a parasitic element due to such a depression.
In the manufacturing method of the sixth aspect, the sidewall consists essentially of the first sidewall and the second sidewall. This further increases the effect of the fifth aspect.
In the manufacturing method of the seventh aspect, at the eighth step, after the third sidewall is formed, the second insulating layer, the sidewall, and the third sidewall, and a predetermined portion of the fourth insulating layer is removed. This further increases the effect of the fifth aspect.
The present invention is directed to solve the aforementioned problems (1) to (3) of the conventional MOSFET. An object of the present invention is to provide a semiconductor device having an SOI structure with no parasitic element at the end portion of a semiconductor layer.
To achieve this object, another object of the present invention is to provide a manufacturing method of such a device, which can prevent formation of a depression causing a parasitic element.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.